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RM0008
General-purpose timer (TIMx)
In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the
UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or
DMA request is sent). This is to avoid generating both update and capture interrupt when
clearing the counter on the capture event.
When an update event occurs, all the registers are updated and the update flag (UIF bit in
TIMx_SR register) is set (depending on the URS bit):
●
●
The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC
register).
The auto-reload active register is updated with the preload value (content of the
TIMx_ARR register). Note that if the update source is a counter overflow, the auto-
reload is updated before the counter is reloaded, so that the next period is the expected
one (the counter is loaded with the new value).
The following figures show some examples of the counter behavior for different clock
frequencies.
Figure 113. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6
CK_INT
CNT_EN
Timer clock = CK_CNT
Counter register
Counter underflow
Counter overflow
Update event (UEV)
Update interrupt flag (UIF)
04
03 02 01 00 01 02 03 04 05 06 05 04 03
1.
Here, center-aligned mode 1 is used (for more details refer to Section 14.4.1: TIMx control register 1 (TIMx_CR1) on
page 355 ).
Figure 114. Counter timing diagram, internal clock divided by 2
CK_INT
CNT_EN
TImer clock = CK_CNT
Counter register
0003
0002 0001
0000
0001
0002
0003
Counter underflow
Update event (UEV)
Update interrupt flag (UIF)
Doc ID 13902 Rev 9
329/995
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